1. The Field of the Invention
The present invention relates to a control circuit and a related method for improving the access time of synchronous DRAM memory. More particularly, the present invention is directed toward decreasing the access time of synchronous DRAM memory through the use of partially asynchronous circuitry.
2. The Relevant Technology
Dynamically refreshable random access memory (DRAM) is currently highly utilized for providing rapid data storage and retrieval in computerized equipment at a reasonable cost. DRAM technology is evolving rapidly. One recent emergence in the DRAM field is the use of synchronous operation of the DRAM control circuitry.
FIGS. 1 through 3 illustrate the use of synchronous circuitry to control a DRAM memory cell array. FIG. 1 is a functional block diagram depiction of a synchronous DRAM circuit. Shown therein is an internal control logic module 12, which receives control commands on pins numbered 14 through 26, and which generates the internal controls for either reading data located on pins denoted DQM through DQ8 into the memory bank or producing data from the memory bank onto the pins DQM through DQ8. Typical DRAM addresses are broken into two portions by an external logic control module (not depicted). These two portions comprise a row address and a column-address in order that a narrower bus width can be used. Also shown in FIG. 1 are two paths for the row and column-addresses which are typically provided on an internal address denoted by pins A0 through A10 by the memory control module. In response to signals from internal control logic module 12, the row address is routed through the row address decoding circuitry including a row address latch 28, a row multiplexer 30, row address buffers 32, and a row address decoder 34. Row multiplexer 30 is used only where more than 1 bank of memory cells is included. This allows for bank switching, which is an improvement gained by the advance to synchronous DRAM. Typically, two memory array banks, bank 0 and bank 1, are multiplexed by row multiplexer 30 in response to the state of address line A10.
The column-address is routed through the column decoding circuitry, including column-address latch 36, burst counter 38, column-address buffer 40, column decoder 42, and sense amplifiers I/O gating module 44. Data is transferred to or from the memory array bank 10 from the data bus, comprising pins DQM through DQ8, through either a data in buffer 46 or a data out buffer 48, as well as a latch 50 and sense amplifiers I/O gating 44. The signals are synchronized with the number 1 clock generator 52 and the number 2 clock generator 54. Mode register 56 is for setting up the memory array bank and control module in one of a predetermined number of functional modes. The refresh circuitry including refresh controller 58, refresh counter 60, and self refresh oscillator and timer 62 provide the dynamic refresh functions necessary at regular intervals to maintain the data voltage level in memory array bank 10.
FIG. 2 is a flow chart describing the operation of the synchronous DRAM and control circuitry of FIG. 1 during a read operation. The process described is a read operation and is discussed for illustration purposes only, as synchronous DRAM read and write operations are commonly known in the art. The first step, denoted at block 60, is the issuance of a read command by the microprocessor or other circuitry which is utilizing memory array bank 10 for storage of data. Throughout this document, generalized names will be given to signals which may also be known by other names. For instance, the read command may also be known as the "memory access command." These commands will be recognizable by those skilled in the art.
The read command is typically received by the memory control module which typically comprises a PC decoding chip set. In the next step, denoted at block 62, the address is issued by the microprocessor onto the address bus lines which communicate between the microprocessor and the memory control module. This address is received by the decoder chip set, which divides the address into two portions. In block 64, the row address portion is transmitted to the memory module of FIG. 1 on the internal address bus denoted by pins A0 through A10 on FIG. 1. Thereafter, the decoder chip set issues a RAS signal to the internal control logic module 12 of the memory module. This alerts the control logic circuitry that a stable address is present on pins A0 through A1. Once again, the term "RAS signal" is a generic term taken from standard DRAM terminology.
In actual operation, a certain combination of signals on pins 18-24 of FIG. 1 are given, and may otherwise be known as the "bank active command." Control logic module 12 then issues the appropriate commands to row address latch 28 and row multiplexer 30, such that the row address can be entered into row address buffers 32 and row decoder 34, and decoded as denoted in block 70.
Thereafter, the proper row address passes into memory array bank 10, and the row is selected as denoted in block 72. Next, the memory control module issues the column-address to the memory module of FIG. 1 where it will be present on pins A0 through A10. This is denoted in block 74. In block 76 it is further denoted that the decoder chip set then issues a CAS signal to control logic module 12 to alert it that a stable column-address is present on pins A0 through A10.
The CAS signal is also a generalized term denoting a specific combination of signals on pins 18 through 24 of FIG. 1, and may otherwise be termed the "read/write signal." The CAS signal must wait a certain amount of time for setup and hold the row-address to the column-address, which is typically about 20 ns and is denoted t.sub.RCD. t.sub.RCD is further lengthened by the necessity of waiting for the occurrence of a synchronizing clock signal, often increasing the delay up to 30 ns.
Thereafter, control logic module 12 generates the internal signals to column-address latch 36 such that the column-address passes through burst counter 38 and into column-address buffer 40 where it is then decoded by column decoder 42. This is depicted by block 80. Once decoded, the column-address passes into memory array bank 10, and the column is selected as depicted in block 82. Once the column has been selected, memory array bank 10 places the requested data on data bus lines DQM through DQ8 through data-out buffer 48, as denoted in block 84. This completes the first read operation. In burst mode, the circuitry will automatically thereafter load a series of adjacently addressed data onto the data bus.
FIG. 3 is a timing diagram depicting the timing of the above-discussed first read operation depicted in FIG. 2. The timing diagram shows the procedure for reading a double burst of information, Dout.sub.m and Dout.sub.M+1 stored in memory array bank 10. Thus, the memory array module is operating in burst mode with a burst of 2. In burst mode, a specified number of addresses will be written in sequence, wherein the addresses are located in memory locations having the same row-address, and having column-addresses varying as M and M+n, wherein n is the specific number of addresses set up in mode register 56 seen in FIG. 1 by a command code at the power-up stage to burst at every memory access.
FIG. 3 shows that the memory module of FIG. 1 completes the first read operation denoted by Dout on line DQ, which is the data line, in four clock cycles. The timing diagram of FIG. 3 shows the sequence of the read command from the time the system is enabled, denoted by a high signal level on signal CKE. The sequence comprises the command line entering an active state, while at the same time the row-address is placed on pins A0 through A9. Thereafter, there is a delay while the command line is in the no operation mode, and while the row-address decoder is decoding the row-address. Next, during clock cycle T1, and after delay t.sub.RCD, discussed above, the column-address is placed on pins A0 through A9. A read command is issued, which corresponds to the issuance of the CAS signal. Following the read command, there is another delay, denoted by no operation on the command line, and denoted with the delay time t.sub.AA, while the column-address is being decoded. Next, the requested data is presented on line DQ and the first read operation is completed. Afterwards, the further burst mode read operations denoted for the first burst Dout.sub.m+1, are conducted.
Synchronous DRAM is a new and emerging technology that is still being improved upon rapidly. Advantages of synchronous DRAM technology are that it is more accurate, with a reduced tendency to misfire from noise on the control lines. Furthermore, synchronous DRAMs are capable of burst addressing and bank switching, as discussed above, to achieve very high speeds. High speed is the key desired trait in the movement to develop improved memory devices. Nevertheless, synchronous DRAM achieves this higher speed at the sacrifice of certain desirable functions of traditional DRAM technology. For instance, synchronous DRAM is presently incapable of fast page mode addressing. Using fast page mode, current asynchronous DRAM can begin column-addressing as soon as a new column-address is present on the column-address bus lines without waiting for a CAS signal and a concurrent synchronizing clock signal. This allows for a faster t.sub.AA time, the time from when a stable column-address is present on the internal address bus lines until the read or write operation is completed.
Asynchronous DRAM technology typically uses automatic transition detection (ATD) to detect when the new column is present so that column-address decoding can begin immediately thereafter. Using ATD in fast page mode in this manner, multiple reads and writes can be achieved one after the other in a pseudo-burst mode. Synchronous DRAM, on the other hand, is tied to the clock and is incapable of performing such a function. Thus, often a whole clock cycle is lost waiting for the column-address strobe (CAS) to signal the presence of a desired stable column-address after delay t.sub.RCD and for CAS to synchronize with the clock so that the decoding of the column-address can begin.
Thus, it becomes apparent that there is a need for a method of improving access times of synchronous DRAM memory to overcome delays, such as the delay between the stable presence of a column-address on the address lines and the generation of a column access strobe signal from the decoder circuitry. Such a step has not been taken in the art, presumably because it would appear to be a step back in the advancement of DRAM technology, which has recently migrated from asynchronous DRAM to synchronous DRAM control, to go back to partially asynchronous DRAM. This is especially the case, as the more efficient burst mode of synchronous DRAM has made the pseudo-burst mode of fast page mode obsolete. From the above discussion, however, it can be seen that it would be a great improvement in synchronous DRAM technology to take an apparent step back and incorporate the asynchronous column-addressing capability of traditional DRAM to the newer synchronous DRAM technology.